View KT8554BD_214248.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

KT8554B/7B
1 CHIP CODECS
INTRODUCTION
The KT8554B/7B are single-chip PCM encoders and decoders (PCM CODECs) and PCM line filters. These devices provide all the functions required to interface a full-duplex voice telephone circuit with a time-division-multiplex (TDM) system. These devices are designed to perform the transmit encoding and receive decoding as well as the transmit and receive filtering functions in PCM system. They are intended to be used at the analog termination of a PCM line or trunk. These devices provide the bandpass filtering of the analog signals prior to encoding and after decoding. These combination devices perform the encoding and decoding of voice and call progress tones as well as the signalling and supervision information. 16-CERDIP
16-DIP300A
FEATURES
* Complete CODEC and filtering system * Meets or exceeds AT&T D3/D4 and CCITT specifications -Law : KT8554B, A-Law : KT8557B * On-chip auto zero, sample and hold, and precision voltage references * Low power dissipation : 60mW (operating) 3mW (standby) * 5V operation * TTL or CMOS compatible * Automatic power down
16-SOP-BD300 -SG
ORDERING INFORMATION
Device KT8554BJ KT8557BJ KT8557BN KT8554BN Package 16-CERDIP 16-DIP-300A 16-SOP-BD300 -SG Operating Temperature - 25 ~ 125C - 25 ~ 70C - 25 ~ 70C
PIN CONFIGURATION
KT8554BD KT8557BD
V BB GNDA
1
16
VF X I + VF X I GS X TS X FS X S DX BCLK
2
15
VF RO V CC FS R DR BCLK
R/CLKSEL
3
14
4
KT8554B/7B
13
5
12
6
11
7
10
X
MCLK R/PDN
8
9
MCLK
X
Fig. 1
KT8554B/7B
1 CHIP CODECS
PIN DESCRIPTION
Pin No 1 2 3 4 5 6 Symbol VBB GNDA VFRO VCC FSR DR BCLKR / CLKSEL MCLKR / PDN MCLKX BCLKX DX FSX TSX GSX VFXI VFXI
+
Description VBB = - 5V 5%. Analog ground. Analog output of the receive power Amp. VCC = +5V 5%. Receive frame sync pulse. 8KHz pulse train. PCM data input. Logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master clock in normal operation and BCLKX is used for both TX and RX directions. Alternately direct clock input available, very from 64KHz to 2.048MHz. When MCLKR is connected continuously high, the device is powered down. Normally connected continusously low, MCLKX is selected for all DAC timing. Alternately direct 1.536MHz/1.544MHz or 2.048MHz clock input available. Must be1.536MHz/1.544MHz or 2.048MHz. May be vary from 64KHz to 2.048MHz but BCLKX is externally tied with MCLKX in normal operation. PCM data output. TX frame sync pulse. 8KHz pulse train. Changed from high to low during the encoder timeslot. Open drain output. Analog output of the TX input amplifier. Used to set gain through external resistor. Inverting input stage of the TX analog signal. Non-inverting input stage of the TX analog signal.
7
8 9 10 11 12 13 14 15 16
ABSOLUTE MAXIMUM RATINGS (Ta = 25oC)
Characteristic Positive Supply Voltage Negative Supply Voltage Voltage at Any Analog Input or Output Voltage at Any Digital Input or Output Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 secs)
Symbol VCC VBB VI (A) Vl (D) Ta T STG T LEAD
Value 7 -7 VCC + 0.3 to VBB - 0.3 VCC + 0.3 to GNDA - 0.3 - 25 to + 125 - 65 to + 150 300
Unit V V V V
o o o
C
C C
KT8554B/7B
1 CHIP CODECS
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, VCC = 5.0V 5%, VBB = - 5.0V 5%, GNDA = 0V, Ta = 0 oC to 70 oC ; typical characteristics specified at VCC = 5.0V, VBB = - 5.0V, Ta = 25 oC ; all signals referenced to GNDA). Characteristic Power Dissipation ICC (DOWN) IBB (DOWN) ICC (A) IBB (A) VIL VIH IIL IIH VOL GNDA VINVIL, all digital inputs VIH VIN VCC DX,IL = 3.2mA SIGR, IL = 1.0mA TSX, IL = 3.2mA,open drain DX, IH = -3.2mA SIGR, IH = -1.0 mA DX, GNDA VO VCC 2.4 2.4 -10 10 2.2 -10 -10 10 10 0.4 0.4 0.4 No Load No Load No Load No Load 0.5 0.05 6.0 6.0 1.5 0.3 9.0 9.0 0.6 mA mA mA mA V V A A V V V V V A Symbol Test Conditions Min Typ Max Unit
Power-Down Current Power-Down Current Active Current Active Current Digital Interface Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage
Output High Voltage Output Current in High Impedance State (TRI-STATE) Analog Interface with Receive Filter Output Resistance Load Resistance Load Capacitance Output DC Offset Voltage Input Leakage Current Input Resistance Output Resistance Load Resistance Load Capacitance Output Dynamic Range Voltage Gain Unity Gain Bandwidth Offset Voltage Common-Mode Voltage Common-Mode Rejection Ratio Power Supply Rejection Ratio
VOH IO (HZ)
RO RL CL VOO (RX) ILKG RI RO RL CL VOD (TX) GV BW VIO (TX) VCM (TX) CMRR PSRR
Pin VFRO VFRO = 2.5V 600
1
3 500
pF mV nA M K pF V V/V
-200 -2.5VV+2.5V, VFXI + or VFXI -2.5VV+2.5V, VFXI + or VFXI Closed loop, unity gain GSX GSX GSX, RL10KW VFXI + to GSX 2.8 5,000 1 -20 CMRRXA > 60dB DC Test DC Test -2.5 60 60 2 10 -200 10 1
200 200 3 50
Analog Interface with Transmit input Amplifier
MHz 20 2.5 mV V dB dB
KT8554B/7B
1 CHIP CODECS
TIMING CHARACTERISTICS
(Unless otherwise noted, VCC = 5.0 5%, VBB = -5.0V 5%, GNDA = 0V, Ta = 0oC to 70 oC; typical characteristics specified at VCC = 5.0V, VBB = -5.0V, Ta = 25 oC; all signals referenced to GNDA.) Characteristic Symbol Test Conditions Depends on the device used and the BCLKR /CLKSEL Pin. MCLKX and MCLKR tPB = 488ns tPB = 488ns Long frame only Short frame only Long frame only Load = 150pF plus 2 LSTTL loads Load = 150pF plus 2 LSTTL loads 50 0 0 80 0 180 140 165 Min Typ 1.536 1.544 2.048 50 50 Max Unit MHz MHz MHz ns ns ns ns ns ns ns ns
Frequency of Master Clocks Rise Time of Bit Clock Fall Time of Bit Clock Holding Time from Bit Clock Low to Frame Sync Holding Time from Bit Clock High to Frame Sync Set-Up Time from Frame Sync to Bit Clock Low Delay Time from BCLKX High to Data Valid Delay Time to TSX Low Delay Time from BCLKX Low to Data Output Disabled Delay Time to Valid Data from FSX or BCLKX, Whichever Comes Later Set-Up Time from DR Valid to BCLKR/X Low Hold Time from BCLKR/X Low to D R Invalid Set-Up Time from FSX/R to BCLKX/R Low Width of Master Clock High Width of Master Clock Low Rise Time of Master Clock Fall Time of Master Clock Set-Up Time from BCLKX High (and FSX In Long Frame Sync Mode) to MCLKX Falling Edge Period of Bit Clock Width of Bit Clock High Width of Bit Clock Low
fMCK tR (BCK) tF (BCK) tH (LFS) tH (HFS) tSU (FBCL) tD (HDV) tD (TSXL) tD (LDD)
tD (VD)
CL = 0pF to 150pF
20
165
ns
tSU (DR BL) tH (BL DR) tSU (FBLS) tW (MCKH) tW (MCKL) tR (MCK) tF( MCK) tSU (BHMF) tCK tW (BCKH) tW (BCKL) VIH = 2.2V VIL = 0.6V Short frame sync pulse (1 or 2 bit clock periods long) (Note1) MCLKX and MCLKR MCLKX and MCLKR MCLKX and MCLKR MCLKX and MCLKR First bit clock after the leading edge of FSX
50 50 50 160 160 50 50
ns ns ns ns ns ns ns
485 160 160
488
15,72 5
ns ns ns
KT8554B/7B
1 CHIP CODECS
TIMING CHARACTERISTICS (Continued)
Characteristic Hold Time from BCLKX/R Low to FSX/R Low Hold Time from 3rd Period of Bit Clock Low to Frame Sync (FSX or FSR) Minimum Width of the Frame Sync Pulse (Low Level) Symbol tH (BLFL) Test Conditions Short frame sync pulse (1 or 2 bit clock periods long) (Note 1) Long frame sync pulse (from 3 to 8 bit clock periods long) 64K bit/s operating mode Min 100 Typ Max Unit ns
tH (3rd )
100
ns
tWFL
160
ns
Note 1 : For short frame sync timing, FSX and FSR must go high while their respective bit clocks are high.
TIMING DIAGRAM
tD (TS X L) tF (MCK) tR (MCK) tW (MCKL) tD (LDD)
tCK
tW (MCKH)
tSU (BHMF)
tH (HFS) tSU (FBLS)
tH (BLFL)
tD (HDV)
tD (LDD)
tH (HFS) tSU (FBCL)
tH (BLFL)
tSU (DR BL)
tH (BLDR) tH (BLDR)
Fig. 2. Short Frame Sync Timing
KT8554B/7B
1 CHIP CODECS
TIMING DIAGRAM
tR (MCK)
(Continued)
tW (MCKL)
tCK
tSU (BHMF)
tW (BCKH) tW (BCKL)
tH (HFS)
tRB
tD (VD) tD (VD)
tD (HDV)
tD (LDD)
tH (HFS)
tSU(FBCK)
tH (3rd)
tSU (DR BL)
tH (BL DR)
tH (BL DR)
Fig. 3 Long Frame Sync Timing
KT8554B/7B
1 CHIP CODECS
TRANSMISSION CHARACTERISTICS
(Unless otherwise specified : Ta = 0oC to 70 oC, VCC = 5V 5%, VBB = -5V 5%, GNDA = 0V, f = 1.02KHz, VIN = 0dBm0, transmit input amplifier connected for unity-gain non-inverting.) Characteristic Amplitude Respons Receive Gain, Absolute GV (ARX) Ta = 25 oC, VCC = 5V, VBB = -5V Input = Digital code sequence for 0dBm0 signal at 1020Hz f = 0Hz to 3000Hz f = 3300Hz f = 3400Hz f = 4000Hz Ta = 0 oC to 70 oC VCC = 5V 5%, VBB = -5V 5% Sinusoidal test method ; reference input PCM code corresponds to an Ideally encoded -10dBm0 signal PCM level = -40dBm0 to +3dBm0 PCM level = -50dBm0 to -40dBm0 PCM level = -55dBm0 to -50dBm0 RL = 600 Nominal 0dBm0 level is 4dBm (600) 0dBm0 Max overload level (3.17dBm0): KT8554B Max overload level (3.14dBm0): KT8557B Ta = 25 oC, VCC = 5V, VBB = -5V Input at GSX = 0dBm0 at 1020Hz f = 16Hz f = 50Hz f = 60Hz f = 200Hz f = 300Hz - 3000Hz f = 3300Hz f = 3400Hz f = 4000Hz f = 4600Hz and up, measure response from 0Hz to 4000Hz Ta = 0 oC to 70 oC VCC = 5V 5%, VBB = -5V 5% Sinusoldal test method Reference level = - 10dBm0 VFXI + = - 40dBm0 to + 3dBm0 VFXI + = - 50dBm0 to - 40dBm0 VFXI + = - 55dBm0 to - 50dBm0 -0.15 -0.15 -0.35 -0.7 0.15 0.15 0.05 0 -14 0.1 0.05 dB dB dB dB dB dB dB Symbol Test Conditions Min Typ Max Unit
Receive Gain, Relative to GV (ARX)
GV (RRX) GV (ARX) /T GV (ARX) /V GV (RXL)
Absolute Receive Gain Variation with Temperature Absolute Receive Gain Variation with Supply Voltage
Receive Gain Variations with Level
Receive Output Drive Level Absolute Levels Max Overload Level
VO (RX) VAL VOL (MAX)
-0.2 -0.4 -1.2 -2.5 1.2276 2.501
0.2 0.4 1.2 2.5
dB dB dB V Vrms VPK
Transmit Gain, Absolute
GV (ATX)
-0.15
0.15 -40 -30 -26 -0.1 0.15 0.05 0 -14 -32 0.1 0.05
dB dB dB dB dB dB dB dB dB dB dB dB
Transmit Gain, Relative to GV (ATX)
GV (RTX)
-1.8 -0.15 -0.35 -0.7
Absolute Transmit Gain Variation with Temperature Absolute Transmit Gain Variation with Supply Voltage Transmit Gain Variations with Level
GV(ATX) /T GV (ATX) /V GV (TXL)
- 0.2 - 0.4 - 1.2
0.2 0.4 1.2
dB dB dB
KT8554B/7B
1 CHIP CODECS
TRANSMISSION CHARACTERISTICS (Continued)
Characteristic Symbol Test Conditions f = 1600Hz f = 500Hz - 1000Hz f = 1000Hz - 1600Hz f = 1600Hz - 2600Hz f = 2600Hz - 2800Hz f = 2800Hz - 3000Hz f = 1600Hz f = 500Hz - 600Hz f = 600Hz - 800Hz f = 800Hz - 1000Hz f = 1000Hz - 1600Hz f = 1600Hz - 2600Hz f = 2600Hz - 2800Hz f = 2800Hz - 3000Hz PCM code equals alternating positive and negative zero, KT8554B PCM code equals, positive zero, KT8557B KT8554B KT8557B f = 0KHz to 100KHz, loop around measurement, VFXI + = 0Vrms VFXI + = 0Vrms, VCC = 5.0VDC + 100mVrms f = 0KHz - 50KHz VFXI + = 0Vrms, VBB = -5.0VDC + 100mVrms f = 0KHz - 50KHz PCM code equals positive zero VCC = 5.0VDC + 100mVrms f = 0Hz - 4000Hz f = 4KHz - 25KHz f = 25KHz - 50KHz PCM code equals positive zero VBB = 5.0VDC + 100mVrms f = 0Hz - 4000Hz f = 4KHz - 25KHz f = 25KHz - 50KHz -40 -30 Min Typ 180 -25 -20 70 100 145 290 195 120 50 20 55 80 130 8 -82 12 74 Max 200 Unit s s s s s s s s s s s s s s
Envelope Delay Distortion with Frequency Receive Delay, Absolute tD (ARX)
Receive Delay, Relative to tD (ARX)
tD (RRX)
Transmit Delay, Absolute
tD (ATX)
90 125 175 315 220 145 75 40 75 105 155 11 -79 15 -67 -53
Transmit Delay, Relative to tD (ATX)
tD (RTX)
Noise Receive Noise, C Message Weighted Receive Noise, P Message Weighted Transmit Noise, C Message Weighted Transmit Noise, P Message Weighted Noise, Single Frequency Positive Power Supply Rejection, Transmit Negative Power Supply Rejection, Transmit
NRXC NRXP NTXC NTXP NSF PSRR
(PTX)
dBrnc0 dBm0p dBrnc0 dBm0p dBm0 dBC
40
PSRR
(NTX)
40
dBC
Positive Power Supply Rejection, Receive
PSRR
(PRX)
40 40 36
dBC dB dB
Negative Power Supply Rejection, Receive
PSRR
(NRX)
40 40 36
dBC dB dB
KT8554B/7B
CMOS INTEGRATED CIRCUIT
TRANSMISSION CHARACTERISTICS (Continued)
Characteristic Symbol Test Conditions Loop around measurement, 0dBm0, 300Hz - 3400Hz input PCM applied to DR, Measure individual image signals at VFRO 4600Hz - 760Hz 7600Hz - 8400Hz 8400Hz - 100,000Hz Sinusoidal test method Level = 3.0dBm0 = 0dBm0 to 30dBm0 = -40dBm0 XMT RCV = -55dBm0 XMT RCV Min typ Max Unit
Spurious Out-of-Band Signals at the Channel Output
SOS
-32 -40 -32
dB dB dB
Distortion 33 26 29 30 14 15 -46 -46 Loop around measurement, VFXI + = -4dBm0 to -21dBm0, two frequencies in the range 300Hz - 3400Hz f = 300Hz - 3400Hz DR = Steady PCM code f = 300Hz - 3400Hz, VFXI = 0V dBC dBC dBC dBC dBC dBC dB dB
Signal to Total Distortion Transmit or Receive Half-Channel
THDTX THDRX
Single Frequency Distortion, Transmit Single Frequency Distortion, Receive Intermodulation Distortion
THD SF (TX) THDSF (RX)
THDIMD
-41
dB
Crosstalk Transmit to Receive Crosstalk, 0dBm0 Transmit Level Receive to Transmit Crosstalk, 0dBm0 Receive Level CT(TX-RX) CT (RX-TX) -90 -90 -75 -70 (Note1) dB dB
Note 1. CT(RX-TX) is measured with a - 40dBm0 activating signal applied at VFXI +
ENCODING FORMAT AT Dx OUTPUT
-Law KT8554B VIN (at GSX) = + Full Scale VIN (at GSX) = 0V VIN (at GSX) = - Full Scale 10000000 11111111 01111111 00000000 A-Law KT8557B 10101010 11010101 01010101 00101010
KT8554B/7B
CMOS INTEGRATED CIRCUIT
APPLICATION CIRCUIT
+5V 0.1F 4 VC C R 2 1 F O SLC R RM I T SLC OI R 4 R 3 14 G X S 15 VX FI3 VR FO 16 VX FI+ PN D 8 ML R N C K/PD 0.1F 2 GD N
-5V
1 VB B D 11 X D6 R ML X 9 CK B L X 10 CK
D X D R CO K LC
KT8554B/7B
B LR L S L 7 C K/ K E C FSS 12 X FS 5 R
R 6
u-lowonly FSX /R
Fig. 4
NOTE 1 : Supposing Desired Line Termination Impedance RL = 600ohm It is 0dBm = 0.77459Vrms NOTE 2 : TX Gain 20 log (R2/R1), R1 + R2 < 100Kohm, or The Correspondence of 1-CHIP CODEC 0dBm 0 = 4dBm.
SELECTION OF MASTER CLOCK FREQUENCY
BCLKR/CLKSEL Clocked 0 1 (or open) KT 8554 1.536 / 1.544 MHz 2.048 MHz 1.536 / 1.544 MHz KT 8557 2.048MHz 1.536 / 1.544 MHz 2.048MHz

▲Up To Search▲

Price & Availability of KT8554BD

	To Download KT8554BD Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .